This invention relates to a negative voltage generator, and more particularly to a negative voltage generator for use in a p-substrate semiconductor device using N-well CMOS technology.
The equivalent circuit diagram of a conventional positive voltage doubler circuit for generating a positive doubled voltage is illustrated in FIG. 1. A charge capacitor Ccharge has a first node 12 connected to one side of switch S4, and a second node 11 connected to one side of switches S2 and S3. A reservoir output capacitor Creservoir has a first node 10 connected to the other side of switch S4, and a second node 13 connected to the other side of switch S2. The potential of the second node 13 of the reservoir capacitor Creservoir will be referred to as Vss. The other sides of switches S1 and S3 are connected together, and the potential at this connection will be referred to as Vdd. The first node 10 of the reservoir capacitor Creservoir is also the output terminal Vout of the positive voltage doubler circuit.
The conventional positive voltage doubler circuit illustrated in FIG. 1 is operated in two phases. During the first phase, switches S1 and S2 are closed while switches S3 and S4 are opened. During this period of time the charge capacitor Ccharge is charged to a potential of (Vddxe2x88x92Vss). This provides an accumulated charge Q in the charge capacitor Ccharge according to the following equation:
Q=(Vddxe2x88x92Vss)*Cchargexe2x80x83xe2x80x83Eq. 1
During the second phase switches S1 and S2 are opened and switches S3 and S4 are closed. All four switch transistors S1-S4 are switched using a control signal, typically generated by an oscillator. The time period of the second phase does not overlap the time period of the first phase. During the second phase, the charge Q that was previously stored in the charge capacitor Ccharge during the first phase is transferred to the reservoir capacitor Creservoir.
A continual cycling between the first phase and the second phase will pump the output voltage level Vout of the first node 10 of the reservoir capacitor Creservoir according to the following equation:
Vout=2*(Vddxe2x88x92Vss)xe2x80x83xe2x80x83Eq. 2
This equation assumes that there is no load present.
A conventional CMOS formation is shown in FIG. 2, which illustrates a typical cross section of a p-type substrate having an n-type isolated well. A p-channel transistor 25 (switch) is formed in an N-well 21 of a p-substrate 22. An n-channel transistor 23 (switch) is also formed in the p-substrate 22.
Inherent to any n-channel transistor are parasitic diodes. The N-well itself 21 forms a parasitic diode 30 with the P-substrate 22. Usually, the substrate 22 is connected to the voltage potential Vss, which is ground in most systems. The N-well 21 can be connected to any potential above Vss as long as the reverse biasing of the junction between the N-well 21 and the p-substrate 22 is less the break down voltage.
Parasitic diodes are also formed between sources and drains of the transistors, and the P-substrate or N-well in which they are formed. The N+ source and drain regions 24, 26 form parasitic diode 28a, 28b with the P-substrate 22. The N+ source and drain regions 24, 26 form the cathodes while the N-well 21 forms the anodes. Similarly, parasitic diodes 29a and 29b are formed in the p-channel transistor 25 between the source and drain regions 27, 20 and the N-well 21.
In the circuit illustrated in FIG. 1, the voltage doubler requires one p-channel switch transistor S4 and three n-channel switch transistors S1, S2 and S3. It is the parasitic diodes 28a and 28b which determine the channel formation of the switches. When switch S4 is a p-channel transistor in an N-well, the N-well can be biased to the output voltage Vout.
In certain circumstances, a negative voltage generator is desirable. However, a negative voltage generator is not preferably made in a p-type substrate having n-type isolated wells by reversing referenced voltages of the positive voltage doubler, because of parasitic diodes.
A conventional negative voltage generator is illustrated in FIG. 3. The operation of the negative voltage generator is similar to that of the conventional positive voltage doubler. A charge capacitor Ccharge has first node 30 connected to one side of switches S5 and S7, and a second node 31 connected to one side of switches S6 and S8. The other side of switch S5 is referenced to the positive voltage level Vdd, and the second side of switch S6 is referenced to the voltage level Vss (usually ground). The other side of switch S7 is connected to Vss.
A reservoir capacitor Creservoir has a first node 32 connected to the Vss potential, and a second node 33 connected to the other side of switch S8. The second node 33 of the reservoir capacitor Creservoir provides the output voltage Vout of the conventional negative voltage generator.
The negative voltage generator operates in two cycles. During the first cycle switches S5 and S6 are closed while switches S7 and S8 are opened. This allows the charge capacitor Ccharge to be charged with a positive voltage of (Vddxe2x88x92Vss) appearing at the first node 30 and a voltage Vss at the second node 31. During the second cycle, which does not overlap the first cycle, switches S5 and S6 are opened and switches S7 and S8 are closed. This allows the charge which was previously stored on the charge capacitor Ccharge to be transferred to the reservoir capacitor Creservoir. The continuous cycling between the first cycle and the second cycle generates a negative voltage with respect to Vss at the output Vout of the negative voltage generator.
The conventional negative voltage generator is not preferably formed in a p-substrate using an N-well process because of the aforementioned parasitic diodes. For example, if switch S8 was made from an n-channel transistor 23 as shown in FIG. 2, the N+drain region 24 would be connected to a negative voltage Vout while the substrate was connected to a higher voltage Vss. The parasitic diode 28b of the transistor will be forward biased, and the output voltage Vout will be clamped to a maximum of one diode voltage drop below Vss. Therefore, the negative voltage generator is conventionally implemented with a P-well CMOS process.
It is an object of the invention to provide a negative voltage generator using N-well CMOS technology which drives a p-channel output driver transistor having a low output impedance.
It is a further object to provide a negative voltage generator using N-well CMOS technology which can generate a voltage more negative than a parasitic diode voltage drop.
To solve these and other objects, a negative voltage generator is provided using an N-well CMOS process which is particularly useful for low voltage applications and low impedance applications.
A positive voltage doubler circuit using N-well CMOS technology is provided in a negative voltage generator. The positive voltage generator charges a load capacitor to a doubled voltage level. The negative voltage generator then implements two cycles by which a negative voltage is generated. The first cycle charges an output capacitor to a potential equal to the difference between the doubled voltage and the original voltage source. A second cycle then changes the positive reference node of the output capacitor to be at ground level, and lets the negative reference node of the output capacitor float to a potential equal in magnitude to the original power source, however it now being a negative voltage with reference to the ground.
The negative voltage generator according to the present invention eliminates the limitation of the achievable negative voltage being the parasitic diode voltage drop which exists when implementing a negative voltage generator using N-well CMOS technology.